www.exar.com xr16m890 single-channel uarts with selectable bus interfaces simplify mixed voltage designs for next generation systems 8-bit (intel/motorola/vlio) uart with 128-byte fifo and integrated level shifters the xr16m890 1 (m890) is a single-channel universal asynchronous receiver and transmitter (uart) with integrated level shifters and 128 bytes of transmit and receive fifos. for flexibility in a mixed voltage environment, the m890 has 4 vcc pins. there is a vcc pin for the core, a vcc pin for the uart signals, a vcc pin for the cpu interface signals and a vcc pin for the gpio signals. the vcc pins for the uart, gpio and cpu interface signals allow for the m890 to interface with devices operating at different voltage levels eliminating the need for external voltage level shifters. the vcc core voltage helps to lower the overall power consumption for applications that use slower data rates. the auto rs-485 half-duplex direction control feature simplifies both the hardware and software for half-duplex rs-485 applications. in addition, the multidrop mode with auto address detection and address byte control features increase the performance by simplifying the software routines. the independent tx/rx baud rate generator feature allows the transmitter and receiver to operate at different baud rates. in addition, the fractional baud rate generator feature provides flexibility for crystal/clock frequencies for generating standard and non-standard baud rates. the m890 has programmable transmit and receive fifo trigger levels, automatic hardware and software flow control, and data rates of up to 24 mbps. power consumption of the m890 can be minimized by enabling the sleep mode. the m890 has a 16550 compatible register set that provide users with operating status and control, receiver error indications, and modem serial interface controls. an internal loopback capability allows onboard diagnostics. the m890 has a selectable intel/motorola/vlio bus interface. note: 1 covered by u.s. patent #5,649,122. features ? integrated level shifters on cpu interface, uart and gpio signals ? intel/motorola/vlio bus interface select ? 24 mbps maximum uart data rate ? up to 16 gpios ? 128-bytes tx and rx fifos ? programmable tx/rx trigger levels ? tx/rx fifo level counters ? independent tx/rx baud rate generator ? fractional baud rate generator ? auto rts/cts hardware flow control ? auto xon/xoff software flow control ? auto rs-485 half-duplex direction control ? multidrop mode w/ auto address detect (rx) ? multidrop mode w/ address byte control (tx) ? sleep mode with automatic wake-up ? infrared (irda 1.0 and 1.1) mode ? 1.62v to 3.63v supply operation ? crystal oscillator or external clock input ? 5v tolerant inputs
www.exar.com e x a r c o r p o r at i o n 48720 kato road fremont, ca 94538 u.s.a. t. +1.510.668.7000 f. +1.510.668.7001 ? 2 010 e x a r c o r p o r at i o n f ly1110 _ x r16 m 8 9 0 xr16m890 single-channel uarts with selectable bus interfaces simplify mixed voltage designs for next generation systems 8-bit (intel/motorola/vlio) uart with 128-byte fifo and integrated level shifters typical applications ? personal digital assistants (pdas) ? cellular phones/data devices ? battery-operated devices ? global positioning system (gps) ? bluetooth block diagram vcc_core intel/ motorola / vlio bus interface vcc_bus 1.62v- 3.63v i/o buffers vcc_uart uart regs fractional brg 128-byte tx fifo 128-byte rx fifo tx rx crystal oscillator/ buffer gpios tx rx rts# cts# a2:a0 d7:d0 (ad7:ad0) cs# ior# iow# (r/w#) int (irq#) reset (reset#) 16/68# xtal1 xtal2 1.62v- 3.63v i/o buffers vlio_en lla # gpio[3:0] flow control en485# enir# gpio[15:4] 1.62v- 3.63v i/o buffers vcc_gpio sleep/pwrdn ordering information p art number package number of gpios operating temperature range xr16m890il32-f qfn-32 4 -40c to +85c XR16M890IL40-F qfn-40 8 -40c to +85c xr16m890im48-f tqfp-48 16 -40c to +85c
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